product brief may 2000 orca ? ORT4622 field-programmable system chip (fpsc) four channel x 622 mbits/s backplane transceiver introduction lucent technologies microelectronics group has developed a solution for designers who need the many advantages of fpga-based design implemen- tation, coupled with high-speed serial backplane data transfer. the 622 mbits/s backplane transceiver offers a clockless, high-speed interface for interde- vice communication on a board or across a back- plane. the built-in clock recovery of the ORT4622 allows for higher system performance, easier-to- design clock domains in a multiboard system, and fewer signals on the backplane. network designers will benefit from the backplane transceiver as a net- work termination device. the backplane transceiver offers sonet scrambling/descrambling of data and streamlined sonet framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary sys- tems. for non-sonet applications, all sonet func- tionality is hidden from the user and no prior networking knowledge is required. embedded core features n implemented in an orca series 3 fpga array. n allows wide range of applications for sonet net- work termination application as well as generic data moving for high-speed backplane data trans- fer. n no knowledge of sonet/sdh needed in generic applications. simply supply data, 78 mhz clock, and a frame pulse. n high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without external clocks. n hsi function uses lucent technologies microelec- tronics groups proven 622 mbits/s serial interface core. n four-channel hsi function provides 622 mbits/s serial interface per channel for a total chip band- width of 2.5 gbits/s (full duplex). n lvds i/os compliant with eia *-644, support hot insertion. n 8:1 data multiplexing/demultiplexing for 77.76 mhz byte-wide data processing in fpga logic. n on-chip phase-lock loop (pll) clock meets b jitter tolerance specification of itu-t recommendation g.958 (0.6 uip-p at 250 khz). n powerdown option of hsi receiver on a per- channel basis. n highly efficient implementation with only 3% over- head vs. 25% for 8b10b coding. n in-band management and configuration. n streamlined pointer processor (pointer mover) for 8 khz frame alignment to system clocks. n built-in boundry scan ( ieee ? 1149.1 jtag). * eia is a re g istered trademark of electronic industries associa- tion. ? ieee is a re g istered trademark of the institute of electrical and electronics en g ineers, inc. table 1. orca ORT4622available fpga lo g ic * the embedded core and interface are not included in the above g ate counts. the usable g ate count ran g e from a lo g ic-onl y g ate count to a g ate count assumin g 30% of the pfus/slics bein g used as rams. the lo g ic-onl y g ate count includes each pfu/slic ( counted as 108 g ates per pfu/slic ) , includin g 12 g ates pre-lut/ff pair ( ei g ht per pfu ) , and 12 g ates per slc/ff pair ( one per pfu ) . each of the four pios per pic is counted as 16 g ates ( two ffs, fast-capture latch, output lo g ic, clk drivers, and i/o buffers ) . pfus used as ram are counted at four g ates per bit, with each pfu capable of implementin g a 32 x 4 ram ( or 512 g ates ) per pfu. device usable s y stem gates * number of luts number of re g isters max user ram max user i/os arra y size number of pfus ORT4622 60k120k 4032 5304 64k 259 18 x 28 504
2 lucent technologies inc. product brief may 2000 four channel x 622 mbits/s backplane transceiver orca ORT4622 fpsc embedded core features (continued) n fifos ali g n incomin g data across all four channels for sts-48 ( 2.5 gbits/s ) operation ( in q uad sts-12 format ) . n 1 + 1 protection supports sts-12/sts-48 redundanc y b y either software or hardware control for protection switch- in g applications. n pseudo-sonet protocol includin g a1/a2 framin g . n sonet scramblin g and descramblin g for re q uired ones densit y ( optional ) . n selected transport overhead ( toh ) b y tes insertion and extraction for interdevice communication via the toh serial link. 5-8098(f) figure 1. orca ORT4622 block diagram 5-8337(f) figure 2. sonet network terminaton application clock/data recovery 4 full- duplex serial channels byte- wide data fpga logic standard fpga i/os lv d s 622 mbits/s data 622 mbits/s data pseudo- sonet framer ? pointer mover ? scrambling ? fifo alignment ? toh processor customer network termination embedded core utopia, ds3, sdl, etc. ORT4622 fpsc adm adm adm adm sonet ring customer backplane
product brief may 2000 lucent technologies inc. 3 four channel x 622 mbits/s backplane transceiver orca ORT4622 fpsc embedded core features (continued) 5-8338(f) figure 3. high-speed backplane data transfer 8 8 8 8 board a ORT4622 fpsc 4 x 622 mbits/s system backplane 78 mh z 8 8 8 8 board b ORT4622 fpsc 78 mh z bus bus
4 4 lucent technologies inc. product brief may 2000 four channel x 622 mbits/s backplane transceiver orca ORT4622 fpsc fpsc hi g hli g hts n implemented as an embedded core in the orca series 3+ fpsc architecture. n allows the user to inte g rate the core with up to 120k g ates of pro g rammable lo g ic ( all in one device ) and provides up to 242 user i/os in addition to the embedded core i/o pins. n fpga portion retains all of the features of the orca series 3 fpga architecture: high-performance, cost-effective, 0.25 m, 5-level metal technology. twin-quad programmable function unit (pfu) architecture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu. supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each programmable logic cell (plc). up to three expressclk inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. dual-use microprocessor interface (mpi) can be used for configuration, as well as for a general- purpose interface to the fpga. glueless interface to i960 ? and powerpc ? processors with user- configurable address space provided. * pal is a trademark of advanced micro devices, inc. ? i960 is a re g istered trademark of intel corporation. ? powerpc is a re g istered trademark of international business machines corporation. programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be com- bined with fpga logic to create complex functions, such as digital phase-locked loops, frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per device. true internal 3-state, bidirectional buses with simple control provided by the slic. 32 x 4 ram per pfu, configurable as single or dual port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. built-in boundary scan ( ieee 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. n high-speed on-chip interface provided between fpga logic and embedded core to reduce bottle- necks typically found when interfacing off-chip. software su pp ort n supported b y orca foundr y software and third- part y cae tools for implementin g orca series 3+ devices and simulation/timin g anal y sis with the embedded core functions. n embedded core confi g uration options and simulation netlists g enerated b y the fpsc confi g uration man- a g er utilit y .
product brief may 2000 lucent technologies inc. 5 four channel x 622 mbits/s backplane transceiver orca ORT4622 fpsc ordering information 5-6435 (f).i device type package type ORT4622 bc number of pins temperature range 432 table 2. voltage options table 3. temperature options table 4. package type options table 5 . orca series 3+ package matrix key: c = commercial, i = industrial. device voltage ORT4622 2.5 v/3.3 v symbol description temperature (blank) commercial 0 c to 70 c i industrial C 40 c to +85 c symbol description bc enhanced ball grid array (ebga) bm plastic ball grid array, multilayer device package 432-pin ebga 680-pin pbgam bc432 bm680 ORT4622 ci ci
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. copyright ? 2000 lucent technologies inc. all rights reserved may 2000 pn00-072fpga (replaces ds99-143fpga-1) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)
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